1. Field of the Invention
The present invention relates to a pattern shape evaluation method and a pattern shape evaluation apparatus utilizing the same and, for example, to a method for evaluating interconnection patterns or photo-resist patterns in a semiconductor device and a pattern shape evaluation apparatus utilizing the same.
2. Background Art
Recently, the patterns of a semiconductor device have been becoming finer ever increasingly, thus resulting in an increase in importance of the pattern shape evaluation. Further, in manufacturing of the semiconductor devices, it is necessary to accurately measure, evaluate, and control the dimensions not only of simple shapes such as line patterns and hole patterns but also of complicated shapes such as line end abutting patterns. Actually, there may be some cases where the patterns would be coupled between the line ends owing to influences such as variations in light exposure/focus value of an exposure machine and accuracies of optical proximity correction (OPC) in lithography process in which pattern is formed.
In general, to evaluate the pattern shapes of a semiconductor device, dimension measurement has been employed using a critical dimension scanning electron microscope (CDSEM). However, this dimension measurement approach by use of the CDSEM will obtain only the distance between two points on the contour line of a pattern but is not able to decide whether the shape of the pattern is acceptable.